FIELD OF THE INVENTION
Dynamic random access memories (DRAMs) are customarily organized in blocks. Each memory block has a number of memory cells that can be selected through word and bit lines. In the customary one-transistor memory cell, a storage capacitor is connected to one of the bit lines through a selection transistor. A control connection of the selection transistor is connected to one of the word lines. The word and bit lines are disposed in the form of a matrix. The memory cells are configured at their points of intersection. Each memory block is delimited on two opposing sides by sense amplifiers. No more than one word line can be selected simultaneously per memory block because a plurality of memory cells would otherwise be connected to the same bit line simultaneously.
To repair faulty DRAMs, different redundancy methods are known in which word lines containing faulty memory cells are replaced by redundant word lines whose memory cells are intact. If appropriate redundancy programming is carried out, when a word address is applied that addresses the faulty word line, the redundant word line is selected instead of the faulty one, and selection of the faulty word line is prevented. The redundant word lines are configured parallel to the normal word lines in each memory block, and are connected to redundant memory cells. The redundant memory cells are similarly connected to the bit lines in the memory block.
A distinction is drawn between intrablock redundancy and interblock redundancy. With intrablock redundancy, only a redundant word line from the same memory block can replace a faulty word line. With interblock redundancy, a redundant word line from another memory block can also replace a faulty word line. While intrablock redundancy ensures that no more than one word line is ever activated within a block by replacing a faulty word line in a block with a redundant word line from the same block, it is possible that with interblock redundancy, in addition to an intact word line in a block being activated, a redundant word line in the same block (replacing a faulty word line in another block at the same instant) is also activated. To benefit from the advantages of interblock redundancy--namely, replacing word lines with redundant word lines from other blocks--the sacrifice must therefore be that only a single word line per group of memory blocks to which interblock redundancy applies is activated at the same instant, instead of one word line per memory block (as in the case of intrablock redundancy).
Because the storage capacitors used in dynamic memories lose their charge as a result of leakage currents, dynamic memories have an inherent property necessitating memory cell refreshing at certain intervals of time. Regular refreshing must be carried out for each memory cell. Because in memories with interblock redundancy not more than one word line is activated per interblock group, the same holds true for refreshing the memory cells. Therefore, refreshing takes a relatively long time.
German Published, Non-Prosecuted Patent Application 42 41 327 A1 describes a dynamic memory having memory cells combined to form blocks, and having bit lines and word lines for selecting the memory cells, the blocks being combined to form a block group.
IEEE Journal of Solid State Circuits, Volume 26, No. 11, Nov. 1, 1991, pages 1486-1491, Shigeru Mori et al., describes a dynamic memory having memory cells which are combined to form blocks and having bit lines and word lines for selecting the memory cells.